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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8111
Features
* Operates at Either STS-3/STM-1 (155.52 Mb/s) or STS-12/STM-4 (622.08 Mb/s) Data Rates * Compatible with Industry ATM UNI Devices * On Chip Clock Generation of the 155.52 Mhz or 622.08 Mhz High Speed Clock * Dual 8 Bit Parallel TTL Interface * SONET/SDH Frame Detection and Recovery
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
* Loss of Signal (LOS) Control * Provides Equipment, Facilities and Split Loopback Modes as well as Loop Timing Mode * Meets Bellcore, ITU and ANSI Specifications for Jitter Performance * Single 3.3V Supply Voltage * Low Power - 1.4 Watts Maximum * 100 PQFP Package
General Description
The VSC8111 is an ATM/SONET/SDH compatible transceiver integrating an on-chip clock multiplication unit (PLL) for the high speed clock and 8 bit serial-to-parallel and parallel-to-serial data conversion. The high speed clock generated by the on-chip PLL is selectable for 155.52 or 622.08 MHz operation. The demultiplexer contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equipment loopback modes and two loop timing modes. The part is packaged in a 100 PQFP with an integrated heat spreader for optimum thermal performance and reduced cost. The VSC8111 provides an integrated solution for ATM physical layers and SONET/SDH systems applications.
VSC8111 Block Diagram
EQULOOP LOSTTL LOSPOL RXDA TAIN+/LOS (Internal Signal) DQ FRAMER OOF FP 8
0 1
1:8 DEMUX
DQ
RXOUT[7:0]
RXCLKIN+/-
0 1 0 1 Divide-by-8 RXLSCKOUT
1 TXDATAOUT+/QD 0 1 TXCLKOUT+/FACLOOP Divide-by-3/12 1 0 1 CMU 0 REFCLK LOS LOOPTIM1 EQULOOP RX50MCK LOOPTIM0 0 Divide-by-8 8:1 MUX QD 8 TXIN[7:0] TXLSCKIN TXLSCKOUT
G52142-0, Rev 4.2
8/31/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Data Sheet
VSC8111
Functional Description
The VSC8111 is designed to provide a SONET/SDH compliant interface between the high speed optical networks and the lower speed User Network Interface (UNI) devices such as the PM5355 S/UNI-622 (or PM5312 STTX). The VSC8111 transmit section converts 8 bit parallel data at 77.76 Mb/s or 19.44 Mb/s to a serial bit stream at 622.08 Mb/s or 155.52 Mb/s, respectively. It also provides a Facility Loopback function which loops the received high speed data and clock directly to the transmit outputs. A Clock Multiplier Unit (CMU) is integrated into the transmit circuit to generate the high speed clock for the serial output data stream from input references frequency of 19.44, 38.88, 51.84 or 77.76 MHz. The CMU can be bypassed by using the receive clock in loop timing mode thus synchronizing the entire part to a single clock (RXCLKIN). The receive section provides the serial-to-parallel conversion, converting 155 Mb/s or 622 Mb/s to an 8 bit parallel output at 19.44 Mb/s or 77.76 Mb/s, respectively. The receive section provides an Equipment Loopback function which will loop the low speed transmit data and clock back through the receive section to the 8 bit parallel data bus and clock outputs. The receive section also contains a SONET/SDH frame detector circuit which is used to provide frame recovery in the serial to parallel converter. The block diagram on page 1 shows the major functional blocks associated with the VSC8111.
Transmit Section
Byte-wide data is presented to TXIN [7:0] and is clocked into the part on the rising edge of TXLSCKIN (refer to Figure 1). The data is then serialized (MSB leading) and presented at the TXDATAOUT+/- pins. TXDATAOUT is clocked out on the falling edge of TXCLKOUT+. The serial output stream is synchronized to the CMU generated clock which is a phase locked and frequency scaled version of the input reference clock. External control inputs B0-B2 and STS12 select the multiply ratio of the CMU and either STS-3 (155 Mb/s) or STS-12 (622 Mb/s) transmission (See Table 2). A divide-by-8 version of the CMU clock (TXLSCKOUT) should be used to synchronize the transmit interface of the UNI device to the transmit input registers on the VSC8111. (See Application Notes, Pg. 22)
Figure 1: Data and Clock Transmit Block Diagram
VSC8111 PM5355
TXDATAOUT+ TXDATAOUTTXCLKOUT+ TXCLKOUT-
QD
QD
TXIN[7:0]
QD
TXLSCKIN
REFCLK
CMU
Divide-by-8
TXLSCKOUT
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52142-0, Rev 4.2
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8111
Receive Section
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
High speed Non-Return to Zero (NRZ) serial data at 155Mb/s or 622Mb/s are received by the RXDATAIN inputs. RXDATAIN is clocked in on the rising edge of RXCLKIN+. See Figure 2. The serial data is converted to byte-wide parallel data and presented on RXOUT[7:0] pins. A divide-by-8 version of the high-speed clock (RXLSCKOUT) should be used to synchronize the byte-serial RXOUT[7:0] data with the receive portion of the UNI device. The receive section also includes frame detection and recovery circuitry which detects the SONET/SDH frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the byte aligned data. The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock cycles before the A1A2 boundary. The OOF input control is a level-sensitive signal, and the VSC8111 will continually perform frame detection and recovery as long as this pin is held high even if 1 or more frames has been detected. Frame detection and recovery occurs when a series of three A1 bytes followed by three A2 bytes has been detected. The parallel output data on RXOUT[7:0] will be byte aligned starting on the third A2 byte. When a frame is detected, a single byte clock period long pulse is generated on FP which is synchronized with the byte-aligned third A2 byte on RXOUT[7:0]. The frame detector sends an FP pulse only if OOF is high or if a frame was detected while OOF was being pulled low.
Figure 2: Data and Clock Receive Block Diagram
VSC8111 DQ RXOUT[7:0] PM5355 DQ
1:8 Serial LOSPOL LOSTTL RXDATAIN+ RXDATAINRXCLKIN+ RXCLKIN0 1 CMU Divide-by-8 DQ to Parallel
DQ
FP
DQ
RXLSCKOUT
Loss of Signal
During a LOS condition, the VSC8111 forces the receive data low which is an indication for any downstream equipment that an optical interface failure has occurred. The receive section is clocked by the transmit section's
G52142-0, Rev 4.2
8/31/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Data Sheet
VSC8111
PLL clock multiplier. The VSC8111 has two TTL inputs LOSTTL and LOSPOL one to force the part into a Loss of Signal state, the other to control the polarity. The LOSTTL and LOSPOL inputs are XNOR'd to generate an internal LOS control signal. See Figure 2. Optics have either a PECL or TTL output, usually called "SD" (Signal Detect) or "FLAG" indicating either a lack of or presence of optical power. Depending on the optics manufactured this signal is either active high or active low polarity. If the optics Signal Detect or FLAG output is a "TTL" signal it should be connected to LOSTTL. If it's a "PECL" signal it should be connected through a "PECL" to "TTL" translator (such as the Motorola "MC100ELT21") which then drives LOSPOL. The LOSTTL input should be tied low if the optics "SD" or FLAG output is active high. If it's active low tie LOSTTL high. Note: LOSPOL and LOSTTL are interchangeable. The follow on part to VSC8111 is the VSC8113, in this device the signal LOSPOL has been changed to LOSPECL a PECL input, which is why LOSTTL is being used as the polarity control input.
Facility Loopback
The Facility Loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set high, the Facility Loopback mode is activated and the high speed serial receive data (RXDATAIN) is presented at the high speed transmit output (TXDATAOUT). See Figure 3. In addition, the high speed receive clock input (RXCLKIN) is selected and presented at the high speed transmit clock output (TXCLKOUT). In Facility Loopback mode the high speed receive data (RXDATAIN) is also converted to parallel data and presented at the low speed receive data output pins (RXOUT [7:0]). The receive clock (RXCLKIN) is also divided down and presented at the low speed clock output (RXLSCKOUT).
Figure 3: Facility Loopback Data Path
RXDATAIN
D
Q
1:8 Serial to Parallel
D
Q
RXOUT[7:0]
RXCLKIN
1
/8
Q D Q D
RXLSCKOUT TXIN[7:0]
TXDATAOUT
0
8:1 Parallel to Serial
TXCLKOUT
1 0 PLL
FACLOOP
Equipment Loopback
The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the paral-
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52142-0, Rev 4.2
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8111
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
lel to serial conversion of the low speed data (TXIN [7:0]) is selected and converted back to parallel data in the receiver section and presented at the low speed parallel outputs (RXOUT [7:0]). See Figure 4. The internally generated 155MHz/622MHz clock is used to generate the low speed receive clock output (RXLSCKOUT). In Equipment Loopback mode the transmit data (TXIN [7:0]) is serialized and presented at the high speed output (TXDATAOUT) along with the high speed transmit clock (TXCLKOUT) which is generated by the on board clock multiplier unit.
Figure 4: Equipment Loopback Data Path
RXDATAIN
DQ
0 1
1:8 Serial to Parallel
D
Q
RXOUT[7:0]
RXCLKIN TXDATAOUT
Q D
0 1
/8
8:1 Parallel to Serial Q D
RXLSCKOUT TXIN[7:0] TXLSCKIN /8 TXLSCKOUT
EQULOOP TXCLKOUT
PLL
Split Loopback
Equipment and facility loopback modes can be enabled simultaneously. See descriptions for equipment and facility loop modes above. The only change is, since they are both active, RXDATAIN will not be deserialized and presented to RXOUT[0:7] and TXIN[0:7] will not be serialized and present to TXDATAOUT.
Figure 5: Split Loopback Datapath
1:8 Serial to Parallel D Q
RXDATAIN
D
Q
0 1
RXOUT[7:0]
RXCLKIN
1
0 1
Q D
/8
8:1 Parallel to Serial Q D
RXLSCKOUT TXIN[[7:0] TXLSCLKIN EQULOOP
TXDATAOUT
0
TXCLKOUT
1 0 PLL
FACLOOP
G52142-0, Rev 4.2
8/31/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Loop Timing
Data Sheet
VSC8111
LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single external source. LOOPTIM1 mode bypasses the REFCLK input and uses the divide-by-8 version of the receive clock as the reference input to the CMU. This mode is selected by asserting the LOOPTIM1 input high. The part is forced out of this mode if it is in the Loss of Signal state or in Equipment Loopback to prevent the CMU from feeding its own clock back. The user needs to set the B[0:2] inputs to select 78MHz operation to match the RXLSCKOUT frequency.
Clock Multiplier Unit
The VSC8111 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector (PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feedback system. The PFD compares the selected divided down version of the 622MHz VCO (select pins B0-B2 select divide-by ratios of 8, 12, 16 and 32, see Table 2) and the reference clock. The integrator provides a transfer function between input phase error and output voltage control. The VCO portion of the PLL is a voltage controlled ring-oscillator with a center frequency of 622MHz. The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the amplifier through the CP1, CP2, CN1 and CN2 pins. The configuration of these external surface mounted capacitors is shown in Figure 6. Table 1 shows the recommended external capacitor values for the configurable reference frequencies. Good analog design practices should be applied to the board design for these external components. Tightly controlled analog ground and power planes should be provided for the PLL portion of the circuitry. The dedicated PLL power (VDDANA) and ground (VSSANA) pins should have quiet supply planes to minimize jitter generation within the clock synthesis unit. This is accomplished by either using a ferrite bead or a C-L-C choke ( filter) on the (VDDANA) power pins. Note: Vitesse recommends a ( filter) C-L-C choke over using a ferrite bead. All ground planes should be tied together using multiple vias.
Table 1: Recommended External Capacitor Values Reference Frequency [MHz]
19.44 38.88 51.84 77.76
Divide Ratio
32 16 12 8
CP
0.1 0.1 0.1 0.1
CN
0.1 0.1 0.1 0.1
Type
X7R X7R X7R X7R
Size
0603/0803 0603/0803 0603/0803 0603/0803
Tol.
+/-10% +/-10% +/-10% +/-10%
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52142-0, Rev 4.2
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8111
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Figure 6: External Integrator Capacitor CP = 0.1F
CP1
CP2
+ -
CN1
CN2
CN = 0.1F
Clock Multiplier Unit
Table 2: Reference Frequency Selection and Output Frequency Control Reference Frequency [MHz]
19.44 38.88 51.84 77.76 19.44 38.88 51.84 77.76
STS12
1 1 1 1 0 0 0 0
B2
1 0 0 0 1 0 0 0
B1
1 1 0 0 1 1 0 0
B0
0 0 1 0 0 0 1 0
Output Frequency [MHz]
622.08 622.08 622.08 622.08 155.52 155.52 155.52 155.52
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VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Table 3: Clock Multiplier Unit Performance Name
RCd RCj RCj RCj RCj RCf OCj OCj OCj OCj OCfrange OCd (1) (2) (3)
Data Sheet
VSC8111
Min
40
Description
Reference clock duty cycle Reference clock jitter (RMS) @ 77.76 MHz ref (1) Reference clock jitter (RMS) @ 51.84 MHz ref (1) Reference clock jitter (RMS) @ 38.88 MHz ref (1) Reference clock jitter (RMS) @ 19.44 MHz ref Reference clock frequency tolerance (2) Output clock jitter (RMS) @ 77.76 MHz ref (3) Output clock jitter (RMS) @ 51.84 MHz ref (3) Output clock jitter (RMS) @ 38.88 MHz ref Output frequency Output clock duty cycle
(3) (1)
Typ
Max
60 13 12 9 5
Units
% ps ps ps ps ppm ps ps ps ps MHz %
-20
+20 8 10 13 15
Output clock jitter (RMS) @ 19.44 MHz ref (3) 620 40
624 60
These Reference Clock Jitter limits are required for the outputs to meet SONET system level jitter requirements (< 10 mUIrms) Needed to meet SONET output frequency stability requirements Measured
Note: Jitter specification is defined utilizing a 12KHz - 5MHz LP-HP single pole filter.
AC Timing Characteristics
Figure 7: Receive High Speed Data Input Timing Diagram
TRXCLK RXCLKIN+ RXCLKINTRXSU RXDATAIN+ RXDATAINTRXH
Table 4: Receive High Speed Data Input Timing Table (STS-12 Operation) Parameter
TRXCLK TRXSU TRXH Receive clock period Serial data setup time with respect to RXCLKIN Serial data hold time with respect to RXCLKIN
Description
Min
250 250
Typ
1.608 -
Max
-
Units
ns ps ps
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G52142-0, Rev 4.2
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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8111
Parameter
TRXCLK TRXSU TRXH Receive clock period
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Table 5: Receive High Speed Data Input Timing Table (STS-3 Operation) Description
Serial data setup time with respect to RXCLKIN Serial data hold time with respect to RXCLKIN
Min
1.5 1.5
Typ
6.43 -
Max
-
Units
ns ns ns
Figure 8: Transmit Data Input Timing Diagram
TPROP
TXLSCKOUT TCLKIN
TXLSCKIN TINSU TINH
TXIN [7:0]
Table 6: Transmit Data Input Timing Table (STS-12 Operation) Parameter
TCLKIN TINSU TINH TPROP
Description
Transmit data input byte clock period Transmit data setup time with respect to TXLSCKIN Transmit data hold time with respect to TXLSCKIN Maximum allowable propagation delay for connecting TXLSCKOUT to TXLSCKIN
Min
1.0 1.0 -
Typ
12.86 -
Max
3.0
Units
ns ns ns ns
Table 7: Transmit Data Input Timing Table (STS-3 Operation) Parameter
TCLKIN TINSU TINH TPROP
Description
Transmit data input byte clock period Transmit data setup time with respect to TXLSCKIN Transmit data hold time with respect to TXLSCKIN Maximum allowable propagation delay for connecting TXLSCKOUT to TXLSCKIN
Min
1.0 1.0 -
Typ
51.44 -
Max
30
Units
ns ns ns ns
Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
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VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Figure 9: Receive Data Output Timing Diagram
Data Sheet
VSC8111
TRXCLKIN RXCLKIN+ RXCLKINTRXLSCK RXLSCKOUT
RXOUT [7:0]
A1
A2
A2
A2
A2
TRXVALID FP
Table 8: Receive Data Output Timing Table (STS-12 Operation) Parameter
TRXCLKIN TRXLSCK TRXVALID TPW Receive clock period Receive data output byte clock period Time data on RXOUT [7:0] and FP is valid before and after the rising edge of RXLSCKOUT Pulse width of frame detection pulse FP
Description
Min
4.0 -
Typ
1.608 12.86 12.86
Max
-
Units
ns ns ns ns
Table 9: Receive Data Output Timing Table (STS-3 Operation) Parameter
TRXCLKIN TRXLSCKT TRXVALID TPW Receive clock period Receive data output byte clock period Time data on RXOUT [7:0] and FP is valid before and after the rising edge of RXLSCKOUT Pulse width of frame detection pulse FP
Description
Min
22 -
Typ
6.43 51.44 51.44
Max
-
Units
ns ns ns ns
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52142-0, Rev 4.2
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8111
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Figure 10: Transmit High Speed Data Timing Diagram
TTXCLK
TXCLKOUTTXCLKOUT+ TSKEW TXDATAOUT+ TXDATAOUTTSKEW
Table 10: Transmit High Speed Data Timing Table (STS-12 Operation) Parameter
TTXCLK TSKEW
Description
Transmit clock period Skew between the falling edge of TXCLKOUT+ and valid data on TXDATAOUT
Min
-
Typ
1.608 -
Max
250
Units
ns ps
Table 11: Transmit High Speed Data Timing Table (STS-3 Operation) Parameter
TTXCLK TSKEW
Description
Transmit clock period Skew between the falling edge of TXCLKOUT+ and valid data on TXDATAOUT
Min
-
Typ
6.43 -
Max
250
Units
ns ps
Data Latency
The VSC8111 contains several operating modes, each of which exercise different logic paths through the part. Table 12 bounds the data latency through each path with an associated clock signal.
Table 12: Data Latency Circuit Mode
Transmit Receive Equipment Loopback Facilities Loopback
Description
Data TXIN [7:0] to MSB at TXDATAOUT MSB at RXDATAIN to data on RXOUT [7:0] Byte data TXIN [7:0] to byte data on RXOUT [7:0] MSB at RXDATAIN to MSB at TXDATAOUT
Clock Reference
TXCLKOUT RXCLKIN TXCLKOUT RXCLKIN
Range of Clock cycles
4-13 24-32 27-35 2
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VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Data Sheet
VSC8111
AC Characteristics
Table 13: PECL and TTL Outputs Parameters TR,TTL TF,TTL TR,PECL TF,PECL Description TTL Output Rise Time TTL Output Fall Time PECL Output Rise Time PECL Output Fall Time Min
-- -- -- --
Typ
2 1.5 350 350
Max
-- -- -- --
Units
ns ns ps ps
Conditions 10-90% 10-90% 20-80% 20-80%
DC Characteristics
Table 14: PECL and TTL Inputs and Outputs Parameters VOH VOL VOCM Description Output HIGH voltage (PECL) Output LOW voltage (PECL) O/P Common Mode Range (PECL) Differential Output Voltage (PECL) Differential Output Voltage (PECL) Input HIGH voltage (PECL) Input LOW voltage (PECL) Differential Input Voltage (PECL) I/P Common Mode Range (PECL) Output HIGH voltage (TTL) Min
-- 0.7
Typ
-- --
Max
VDD - 0.9V --
Units
V V
Conditions -- -- --
1.1
--
VDD - 1.3V
V
VOUT75
600
--
1300
mV
75 to VDD - 2.0 V
VOUT50
600
--
1300
mV
50 to VDD - 2.0 V -- -- -- -- IOH = -1.0 mA
VIH VIL
VIN
1.5 0 400 1.5 - VIN/2 2.4
-- -- -- -- --
VDD - 1.0V -- 1600
V V mV V V
VICM VOH
VDD - 1.0 - VIN/2
--
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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8111
Table 14: PECL and TTL Inputs and Outputs Parameters VOL VIH VIL IIH IIL Description Output LOW voltage (TTL) Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Min
-- 2.0 0 -- --
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Typ
-- -- -- 50 --
Max
0.5 5.5 0.8 500 -500
Units
V V V A A
Conditions IOL = +1.0 mA -- -- 2.0V< VIN < 5.5V,
Typical@2.4V
-0.5V < VIN < 0.8V
Power Dissipation
Table 15: Power Supply Currents (Outputs Open) Parameter
IDD PD Power dissipation
Description
Power supply current from VDD
Typ
355 1.2
(Max)
403 1.4
Units
mA W
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VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Data Sheet
VSC8111
Absolute Maximum Ratings(1)
Power Supply Voltage (VDD) Potential to GND .................................................................................-0.5V to +4V DC Input Voltage (PECL inputs) ............................................................................................ -0.5V to VDD +0.5V DC Input Voltage (TTL inputs) .........................................................................................................-0.5V to 5.5V DC Output Voltage (TTL Outputs)........................................................................................ -0.5V to VDD + 0.5V Output Current (TTL Outputs) ................................................................................................................ +/-50mA Output Current (PECL Outputs)............................................................................................................... +/-50mA Case Temperature Under Bias .........................................................................................................-55o to +125oC Storage Temperature.....................................................................................................................-65oC to +150oC Maximum Input ESD (Human Body Model).............................................................................................. 1500 V
Note: Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability.
Recommended Operating Conditions
Power Supply Voltage (VDD) .................................................................................................................+3.3V 5 % Commercial Operating Temperature Range* (T) .................................................................................. 0o to 70oC Extended Operating Temperature Range* (T)..................................................................................... 0o to 110oC Industrial Operating Temperature Range* (T) ................................................................................... -40o to 85oC
* Lower limit of specification is ambient temperature and upper limit is case temperature.
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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8111
Package Pin Description
Table 16: Pin Definitions Signal
FACLOOP VDD N/C RESET LOOPTIM0 B0 B1 B2 VDD TXDATAOUT+ TXDATAOUTVSS TXCLKOUT+ TXCLKOUTVDD N/C N/C VSS RXCLKIN+ RXCLKINVDD OOF N/C RXDATAIN+ RXDATAINNC NC VDD NC N/C
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
I/O
I
Level
TTL +3.3V
Pin Description
Facility loopback, active high +3.3V Power Supply No connection
I I I I I
TTL TTL TTL TTL TTL +3.3V
Resets frame detection, dividers, controls, and tristates TTL outputs; active high Enable loop timing operation; active HIGH Reference clock select, refer to table 2 Reference clock select, refer to table 2 Reference clock select, refer to table 2 +3.3V Power Supply Transmit output, high speed differential data + Transmit output, high speed differential data Ground Transmit high speed clock differential output+ Transmit high speed clock differential output+3.3V Power Supply No connection No connection
O O
PECL PECL GND
O O
PECL PECL +3.3V
GND I I PECL PECL +3.3V I TTL
Ground Receive high speed differential clock input+ Receive high speed differential clock input+3.3V Power Supply Out Of Frame; Frame detection initiated with high level No connection
I I
PECL PECL
Receive high speed differential data input+ Receive high speed differential data inputNo connection No connection
+3.3V
+3.3V Power Supply No connection No connection
G52142-0, Rev 4.2
8/31/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 15
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Table 16: Pin Definitions Signal
VDD N/C RX50MCK VSS RXOUT0 RXOUT1 VSS RXOUT2 RXOUT3 VSS RXOUT4 RXOUT5 VSS RXOUT6 RXOUT7 VSS RXLSCKOUT FP VDD N/C CHNLEN LOSTTL LOSPOL VDD VSS REFCLK LOOPTIM1 VDD VSSA VSSA N/C N/C
Data Sheet
VSC8111
Pin Description
+3.3V Power Supply No connection
Pin
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
I/O
Level
+3.3V
O
TTL GND
Constant 51.84Mhz reference clock output, derived from the Clock Multiplier Unit Ground Receive output data bit0 Receive output data bit1 Ground Receive output data bit2 Receive output data bit3 Ground Receive output data bit4 Receive output data bit5 Ground Receive output data bit6 Receive output data bit7 Ground Receive byte clock output Frame detection pulse +3.3V Power Supply No connection
O O
TTL TTL GND
O O
TTL TTL GND
O O
TTL TTL GND
O O
TTL TTL GND
O O
TTL TTL +3.3V
I I I
TTL TTL TTL +3.3V GND
Tie Low (VSS) for normal operation Loss of Signal Control Loss of Signal Polarity +3.3V Power Supply Ground Reference clock input, refer to table 3 Enable loop timing operation; active HIGH +3.3V Power Supply Analog Ground (CMU) Analog Ground (CMU) No connection No connection
I I
TTL TTL +3.3V GND GND
Page 16
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52142-0, Rev 4.2
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8111
Table 16: Pin Definitions Signal
CP1 CN1 CN2 CP2 VDDA VDDA VDDA VSSA VSSA VSS N/C N/C VSS VDD N/C N/C N/C N/C VDD TXLSCKOUT TXLSCKIN VSS TXIN7 TXIN6 VSS TXIN5 TXIN4 N/C TXIN3 TXIN2 VSS TXIN1 TXIN0
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Pin
63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
I/O
Level
Analog Analog Analog Analog +3.3V +3.3V +3.3V GND GND GND
Pin Description
CMU external capacitor (see Figure 6) CMU external capacitor (see Figure 6) CMU external capacitor (see Figure 6) CMU external capacitor (see Figure 6) Analog Power Supply (CMU) Analog Power Supply (CMU) Analog Power Supply (CMU) Analog Ground (CMU) Analog Ground (CMU) Ground No connection No connection
GND +3.3V
Ground +3.3V Power Supply No connection No connection No connection No connection
+3.3V O I TTL TTL GND I I TTL TTL GND I I TTL TTL
+3.3V Power Supply Transmit byte clock out Transmit byte clock in Ground Transmit input data bit7 Transmit input data bit6 Ground Transmit input data bit5 Transmit input data bit4 No connection
I I
TTL TTL GND
Transmit input data bit3 Transmit input data bit2 Ground Transmit input data bit1 Transmit input data bit0
I I
TTL TTL
G52142-0, Rev 4.2
8/31/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 17
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Table 16: Pin Definitions Signal
N/C STS12 N/C VDD EQULOOP
Data Sheet
VSC8111
Pin Description
No connection
Pin
96 97 98 99 100
I/O
Level
I
TTL
155Mb/s or 622Mb/s mode select, refer to table 2 No connection
+3.3V I TTL
+3.3V Power Supply Equipment loopback, active high
Page 18
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52142-0, Rev 4.2
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8111
Package Information
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
100 PQFP Package Drawings
TOP VIEW
D D1 PIN 100 PIN 1 (NOTE 2) RAD 2.92 .50 (2X) EXPOSED HEATSINK (NOTE 2)
Key
A A1 A2 D D1 E
E1
mm
3.40 0.25 2.7 17.20 14.00 23.20 20.00 0.80 0.65 0.30 0-7 .30 .2 15 15
Tolerance
MAX MIN. .10 .20 .10 .20 .10 .2 NOM .10 +0/-.1 NOM
E1 L e b R R1 2 3
9.0 X 9.0 (N0TE 2)
PIN 30
(NOTE 2) 2.54.50 (2X)
PIN 50
A2
e
R
E
R1
6 4
2
A
NOTES: 0.17 MAX (1) Drawings not to scale. (2) Two styles of exposed heat spreaders may be used; square or oval. (3) All units in millimeters unless otherwise noted
0.25
A1
L
3
b
Package #: 101-202-4 Issue #: 2
G52142-0, Rev 4.2
8/31/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 19
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Data Sheet
VSC8111
The VSC8111 is manufactured in a 100PQFP package which is supplied by two different vendors. The critical dimensions in the drawing represent the superset of dimensions for both packages. The significant difference between the two packages is in the shape and size of the heatspreader which needs to be considered when attaching a heatsink.
Package Thermal Characteristics
The VSC8111 is packaged in a thermally enhanced 100PQFP with an embedded heat sink. The heat sink surface configurations are shown in the package drawings. With natural convection, the case to air thermal resistance is estimated to be 27.5oC/W. The air flow versus thermal resistance relationship is shown in Table 17.
Table 17: Theta Case to Ambient versus Air Velocity Air Velocity (LFPM)
0 100 200 400 600
Case to air thermal resistance oC/W
27.5 23.1 19.8 17.6 16
Junction to case thermal resistance is 1.2 oC/W.
Page 20
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52142-0, Rev 4.2
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8111
Ordering Information
The order number for this product are: Part Number VSC8111QB: VSC8111QB1 VSC8111QB2
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Device Type 155Mb/s-622Mb/s Mux/Dmux with CMU in 100 Pin PQFP Commercial Temperature, 0C ambient to 70C case 155Mb/s-622Mb/s Mux/Dmux with CMU in 100 Pin PQFP Extended Temperature, 0C ambient to 110C case 155Mb/s-622Mb/s Mux/Dmux with CMU in 100 Pin PQFP Industrial Temperature, -40C ambient to 85C case
Notice
Vitesse Semiconductor Corporation reserves the right to make changes in its products specifications or other information at any time without prior notice. Therefore the reader is cautioned to confirm that this datasheet is current prior to placing orders. The company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product.
Warning
Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited.
G52142-0, Rev 4.2
8/31/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 21
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Data Sheet
VSC8111
Application Notes
Interconnecting the Byte Clocks (TXLSCKOUT and TXLSCKIN)
The byte clock (TXLSCKOUT and TXLSCKIN) on the VSC8111 has been brought off-chip to allow as much flexibility in system-level clocking schemes as possible. Since the byte clock (TXLSCKOUT) clocks both the VSC8111 and the UNI devices, it is important to pay close attention to the routing of this signal. The UNI device in general is a CMOS part which can have very wide spreads in timing (1-11ns clock in to parallel data out for the PM5355), which utilizes most of the 12.86ns period (at 78MHz), leaving little for the trace delays and set-up times required to interconnect the 2 devices. The VSC8111 and the UNI device should be placed as close to each other as possible to provide maximum setup and hold time margin at the inputs of the VSC8111. Figure 11 suggests two different ways of routing the TXLSCKOUT-to-TXLSCKIN clock trace when used in a 622MHz mode; which ever method is used, the transmission line trace impedance should be no lower than 75 ohms.
Figure 11: Interconnecting the Byte Clocks
VSC8111 TXIN[7:0] PM5355 POUT[7:0]
TXLSCKIN (1) TXLSCKOUT Ttrace (2) TCLK
(1) TXLSCKOUT and TXLSCKIN are tied together at the pins of the VSC8111. This provides a setup and hold time margin for the TXIN input of * Tsu,margin = Tclk - TTCLK-POUT,max(PM5355) - Tsu,min(VSC8111) - 2xTtrace = 0.86ns - 2xTtrace * Thold,margin = TTCLK-POUT,min(PM5355) - Thold,min(VSC8111) + 2xTtrace = 2xTtrace (2) TXLSCKOUT is daisy chained to the UNI device and then routed back to the VSC8111 along with the byte data. This interface provides a setup and hold time margin for the TXIN input of * Tsu,margin = Tclk - TTCLK-POUT,max(PM5355) - Tsu,min(VSC8111) = 0.86ns * Thold,margin = TTCLK-POUT,min(PM5355) - Thold,min(VSC8111) = 0ns Option (2) does not provide any hold time margin, while option (1) requires the one-way trace delay (Ttrace) to be less than 0.43ns (~3 inches).
Page 22
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52142-0, Rev 4.2
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8111
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Important note: The 11 ns max Tpd on the PM5355 assumes a 50pf load @ 60ps/pf, therefore 3 ns of the max delay is due to loading. The VSC8113 input (TXLSCKIN) plus package is about 6pf. Assuming about 1 pf/ inch of 75 ohm trace on FR4 plus the VSC8113 6pf load, the user would in most cases choose option 1.
AC Coupling and Terminating High-speed PECL I/Os
The high speed signals on the VSC8111 (RXDATAIN, RXCLKIN, TXDATAOUT, TXCLKOUT) use 3.3V PECL levels which are essentially ECL levels shifted positive by 3.3 volts. The PECL I/Os are referenced to the VDD supply (VDD) and are terminated to ground. Since most optics modules use either ECL or 5.0V PECL levels, the high speed ports need to be either AC-coupled to overcome the difference in dc levels, or DC translated (DC level shift). The PECL receiver inputs of the VSC8111 are internally biased at VDD/2. Therefore, AC-coupling to the VSC8111 inputs is accomplished by providing the pull-down resistor for the open-source PECL output and an AC-coupling capacitor used to eliminate the DC component of the output signal. This capacitor allows the PECL receivers of the VSC8111 to self-bias via its internal resistor divider network (see Figure 13). The PECL output drivers are capable of sourcing current but not sinking it. To establish a LOW output level, a pull-down resistor, traditionally connected to VDD-2.0V, is needed when the output FET is turned off. Since VDD-2.0V is usually not present in the system, the resistor should be terminated to ground for convenience. The VSC8111 output drivers should be either AC-coupled to the 5.0V PECL inputs of the optics module, or translated (DC level shift). Appropriate biasing techniques for setting the DC-level of these inputs should be employed. The DC biasing and 50 ohm termination requirements can easily be integrated together using a thevenin equivalent circuit as shown in Figure 12. The figure shows the appropriate termination values when interfacing 3.3V PECL to 5.0V PECL. This network provides the equivalent 50 ohm termination for the high speed I/Os and also provides the required dc biasing for the receivers of the optics module. Table 18 contains recommended values for each of the components.
Figure 12: AC Coupled High Speed I/O
+3.3V DRIVER (Optics Module) PC Board Trace R1 GND GND Note: Only one side of a differential signal is shown. C1 PC Board Trace R2 GND C2 VSC8111 PECL I/O +5.0V R3 RECEIVER (Optics Module)
R4 GND
G52142-0, Rev 4.2
8/31/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 23
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Table 18: AC Coupling Component Values Component
R1 R2 R3 R4 C1, C2, C3, C4
Data Sheet
VSC8111
Value
270 ohms 75 ohms 68 ohms 190 ohms .01uf High Frequency
Tolerance
5% 5% 1% 1% 10%
TTL Input Structure
The TTL inputs of the VSC8111 are 3.3V TTL which can accept 5.0V TTL levels within a given set of tolerances (see Table 14). The input structure, shown in Figure 13, uses a current limiter to avoid overdriving the input FETs.
Layout of the High Speed Signals
The routing of the High Speed signals should be done using good high speed design practices. This would include using controlled impedance lines (50 ohms) and keeping the distance between components to an absolute minimum. In addition, stubs should be kept at a minimum as well as any routing discontinuities. This will help minimize reflections and ringing on the high speed lines and insure the maximum eye opening. In addition the output pull down resistor R2 should be placed as close to the VSC8111 pin as possible while the AC-coupling capacitor C2 and the biasing resistors R3, R4 should be placed as close as possible to the optics input pin. The same is true on the receive circuit side. Using small outline components and minimum pad sizes also helps in reducing discontinuities.
Ground Planes
The ground plane for the components used in the High Speed interface should be continuous and not sectioned in an attempt to provide isolation to various components. Sectioning of the ground planes tends to interfere with the ground return currents on the signal lines. In addition, the smaller the ground planes the less effective they are in reducing ground bounce noise and the more difficult to decouple. Sectioning of the positive supplies can provide some isolation benefits.
Analog Power Supplies
Good analog design practices should be applied to the board design for the analog ground and power planes. The dedicated PLL power (VDDA) and ground (VSSA) pins need to have quiet supply planes to minimize jitter generation within the clock synthesis unit. This is accomplished by either using a ferrit bead or a CL-C choke ( filter).
Page 24
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52142-0, Rev 4.2
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8111
VDD +3.3 V
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Figure 13: Input Structures
VDD +3.3 V
INPUT INPUT
Current Limit
R
INPUT
R GND GND
All Resistors 3.3K
REFCLK and TTL Inputs
High Speed Differential Input (RXDATAIN+/RXDATAIN-) (RXCLKIN+/RXCLKIN-)
G52142-0, Rev 4.2
8/31/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 25
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Data Sheet
VSC8111
Page 26
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52142-0, Rev 4.2
8/31/98

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